1. Field of the Invention
This invention relates to a precision polishing apparatus for highly accurately polishing the surface of a substrate such as a wafer on which dielectric material layers of SiO.sub.2 or the like are laminated in the process of manufacturing a semiconductor device, and a semiconductor device manufacturing method using the same.
2. Related Background Art
In recent years, the high minuteness of semiconductor devices has advanced and the accuracy of the order of submicron has been required of the line widths of minute patterns. Along with this, the technique of highly accurately flattening the surface of a substrate such as a wafer on which wiring or dielectric material layers are laminated has become necessary, and it is said that chemical reaction is concerned in working, and a precision polishing apparatus adopting a polishing method called mechano-chemical polishing, chemical-mechanical polishing, mechano-chemical wrapping or the like has been developed.
Referring to FIG. 14 of the accompanying drawings which shows a precision polishing apparatus according to the prior art, this apparatus has a polishing head 102 for adsorbing and holding a pair of wafers W.sub.0 in such a manner that the polished surfaces thereof face downward and conveying them along a guide 101, a loading portion 103 and a wafer centering portion 104 disposed in series in the direction of conveyance of the wafers, a polishing portion 105 for rotating a polishing pad 105a on a stool, a wafer rinsing portion 106, a wafer reversing portion 107 and an unloading portion 108.
Wafers W.sub.0 contained in a loading cassette G.sub.1 and carried in from the preceding step are taken out of the loading cassette G.sub.1 in the loading portion 103, and are subjected to centering in the centering portion, whereafter the wafers are adsorbed by the polishing head 102 and conveyed to the polishing portion 105. In the polishing portion 105, each wafer W.sub.0 is lightly urged against the surface of the rotating polishing pad 105a and the polishing head 102 is caused to cross along the diameter of the polishing pad 105a to thereby polish the lower surface (the polished surface) of each wafer W.sub.0. The polishing head 102 which has crossed the polishing pad 105a is continuedly moved along the guide 101 and arrives at the wafer rinsing portion 106, where rinsing liquid is blown from nozzles 106a against the polished surfaces of the wafers W.sub.0 to thereby remove any byproduct of polishing. The wafer reversing portion 107 reverses the rinsed wafers W.sub.0 and transports them to the unloading portion 108. In the unloading portion 108, the wafers W.sub.0 are received into an unloading cassette G.sub.2 and sent out to the next step.
The polishing head 102 is suspended from a top frame 102a movable above the wafer centering portion 104, the polishing portion 105, the wafer rinsing portion 106, etc., and one end of the top frame 102a is supported for reciprocal movement along the guide 101 and the other end of the top frame 102a is connected to a driving portion 102b. The top frame 102a having the polishing head 102 suspended therefrom is reciprocally moved along the guide 101 by the driving of the driving portion 102b. The polishing portion 105 has a brushing device 105b and a hand shower 105c for cleaning the surface of the polishing pad 105a.
As described above, design is made such that the polishing and succeeding rinsing step of the wafers W.sub.0 continuously sent in from the preceding step are automatically executed and the wafers are sent out to the next step. Also, the work of cleaning the surface of the polishing pad 105a can be done efficiently during the time until the polishing head 102 is moved in the opposite direction and returned from the unloading portion 108 to the loading portion 103.
On the other hand, FIG. 15 of the accompanying drawings is a flow chart showing the polishing process described in Japanese Patent Application Laid-Open No. 2-257629.
Specifically, a semiconductor substrate (bare silicon wafer) subjected to primary polish which is rough polish is rinsed and dried, whereafter the measurement of the polished state as to whether the semiconductor substrate has unevenness of a predetermined value or greater is effected, and only a semiconductor substrate free of unevenness of a predetermined value or greater is sent to secondary polish which is finishing polish, and a semiconductor substrate having unevenness is subjected to partial polish which will be described later.
That is, the semiconductor substrate subjected to primary polish usually has more or less unevenness on the surface thereof due to the properties of the polishing cloth or the properties of the semiconductor substrate itself or the irregularity of the pressure force. If the degree of the unevenness is such as being capable of being normally subjected to secondary polish, there will be no hindrance even if the semiconductor substrate is sent to the secondary polishing step. However, if the unallowable uneven state is not changed even by secondary polish or it is foreseen for the unevenness to further become unallowable, some treatment should be adopted before the semiconductor substrate is sent to the secondary polishing step. So, this example of the prior art is such that whether there is unallowable unevenness is determined and if there is unallowable unevenness, the semiconductor substrate is subjected to partial polish as described above.
The above-mentioned measurement of the polished state is such that when there are recesses and projections on the polished surface of the semiconductor substrate, the position, area, height, etc. of the projection are put out to thereby form an interference fringe, for example, by a laser, and this interference fringe is analyzed to detect the position, area and height of each region and on the basis thereof, the polishing head is controlled or contour lines are put out by image processing or the like. Specifically, the measurement is effected in such a manner that the surface configuration accuracy of the semiconductor substrate is measured with the back thereof as the standard.
Thus, the measurement of the polished state is effected and any semiconductor substrate of unallowable polish accuracy is sent to the partial polishing step which will be described next.
This partial polishing step partially polishes only a projection to an allowable height when the projection has an unallowable height.
Specifically, the result of the accuracy measurement and an actual semiconductor substrate are made to correspond to 1:1 and as shown in FIG. 16 of the accompanying drawings, the semiconductor substrate 301 is fixedly held on a stool 305, and a small polishing head 304 is controlled and moved by the NC control system correspondingly to the result of the accuracy measurement. The shape of a polishing pad 303 attached to the lower surface of the polishing head 304 may preferably be a circle of which the diameter is 1/10 to 1/20 of the diameter of the semiconductor substrate, and the polishing movement is effected with the polishing head being moved back and forth and to right and left in a horizontal direction while being rotated. The partial polish may preferably be done with the polished surface facing downward to prevent the attack of the semiconductor substrate by polishing liquid (slurry). Thus, the projection on the semiconductor substrate 301 is scraped off by a predetermined amount and rinsed, and the accuracy measurement is effected. By this accuracy measurement, only a semiconductor substrate having allowable surface polish accuracy is sent to secondary polish and on the other hand, a semiconductor substrate of unallowable surface polish accuracy even by the partial polish is again sent to partial polish.
The above-described example of the prior art may be suitable for a case where of relatively large recesses and projections, the projections are flatly polished with the back of a semiconductor wafer as the standard as when the semiconductor wafer before a semiconductor device is manufactured is to be polished.
However, in the case of the polishing of metallic film which is wiring or the polishing of inter-layer insulating film, it is not always good if the surface only becomes flat with the back of the wafer as the standard. Rather such polish is sometimes desired that the same film thickness is provided following the wiring pattern on the ground or the recess and projection of the transistor portion. When the wafer is subjected to such polish, the polished state of the surface of the wafer creates minute recesses and projections. Accordingly, the alternative to effect partial polish or effect secondary polish after determination as in the example of the prior art cannot be said to be suitable for the polishing of a substrate on which an element such as a transistor is formed.
Also, in the example of the prior art, a hard foreign substance may attach to the pad during the steps of secondary polish and tertiary polish to create a new flaw.
So, we have tried a method of manually returning a wafer whose defect has been detected to the primary polishing portion and repeating all the above-described steps, or adding a wafer defect removing device to the downstream side of the tertiary polishing station, and effecting the re-polishing or rinsing of the wafer there to thereby reclaim the defective wafer.
However, it has been found that the defect of a wafer detected by inspection is often, in addition to a flaw on the polished surface requiring re-polishing, a stain by the attachment of the byproduct of polishing such as polishing powder or simply the remain of rinsing liquid due to insufficient drying at the final step, and does not always need re-polishing.
If as described above, a wafer which does not require re-polishing is manually returned to the primary polishing portion of the precision polishing apparatus or manually sent into the wafer defect removing device discrete from the polishing apparatus and re-polished, there is a trouble such as a new defect created at the re-polishing step, in addition to a reduction in throughput due to the addition of an unnecessary polishing step, and as a result, the manufacturing cost of a semiconductor device or the like is considered to rise.